Renesas Electronics /R7FA6M3AH /SPI0 /SPCMD2

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Interpret as SPCMD2

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)CPHA 0 (0)CPOL 0 (00)BRDV 0 (000)SSLA0 (0)SSLKP 0 (0000)SPB0 (0)LSBF 0 (0)SPNDEN 0 (0)SLNDEN 0 (0)SCKDEN

SLNDEN=0, CPHA=0, SSLA=000, SPNDEN=0, BRDV=00, LSBF=0, SPB=0000, SSLKP=0, SCKDEN=0, CPOL=0

Description

SPI Command Register 2

Fields

CPHA

RSPCK Phase Setting

0 (0): Data sampling on odd edge, data variation on even edge

1 (1): Data variation on odd edge, data sampling on even edge

CPOL

RSPCK Polarity Setting

0 (0): RSPCK is low when idle

1 (1): RSPCK is high when idle

BRDV

Bit Rate Division Setting

0 (00): These bits select the base bit rate

1 (01): These bits select the base bit rate divided by 2

2 (10): These bits select the base bit rate divided by 4

3 (11): These bits select the base bit rate divided by 8

SSLA

SSL Signal Assertion Setting

0 (others): Setting prohibited

0 (000): SSL0

1 (001): SSL1

2 (010): SSL2

3 (011): SSL3

SSLKP

SSL Signal Level Keeping

0 (0): Negate all SSL signals on completion of transfer

1 (1): Keep SSL signal level from the end of transfer until the beginning

SPB

RSPI Data Length Setting

0 (others): 8bits

0 (0000): 20 bits

1 (0001): 24 bits

2 (0010): 32 bits

3 (0011): 32 bits

8 (1000): 9 bits

9 (1001): 10 bits

10 (1010): 11 bits

11 (1011): 12 bits

12 (1100): 13 bits

13 (1101): 14 bits

14 (1110): 15 bits

15 (1111): 16 bits

LSBF

RSPI LSB First

0 (0): MSB first

1 (1): LSB first

SPNDEN

RSPI Next-Access Delay Enable

0 (0): A next-access delay of 1 RSPCK + 2 PCLK

1 (1): A next-access delay is equal to the setting of the RSPI next-access delay register (SPND)

SLNDEN

SSL Negation Delay Setting Enable

0 (0): An SSL negation delay of 1 RSPCK

1 (1): An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND)

SCKDEN

RSPCK Delay Setting Enable

0 (0): An RSPCK delay of 1 RSPCK

1 (1): An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD)

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